112 lines
4.0 KiB
C
112 lines
4.0 KiB
C
/* FPU control word bits. Mips version.
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Copyright (C) 1996-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Olaf Flebbe and Ralf Baechle.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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/* MIPS FPU floating point control register bits.
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*
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* 31-25 -> floating point conditions code bits 7-1. These bits are only
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* available in MIPS IV.
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* 24 -> flush denormalized results to zero instead of
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* causing unimplemented operation exception. This bit is only
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* available for MIPS III and newer.
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* 23 -> Condition bit
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* 22-21 -> reserved for architecture implementers
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* 20 -> reserved (read as 0, write with 0)
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* 19 -> IEEE 754-2008 non-arithmetic ABS.fmt and NEG.fmt enable
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* 18 -> IEEE 754-2008 recommended NaN encoding enable
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* 17 -> cause bit for unimplemented operation
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* 28 -> cause bit for invalid exception
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* 27 -> cause bit for division by zero exception
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* 26 -> cause bit for overflow exception
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* 25 -> cause bit for underflow exception
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* 24 -> cause bit for inexact exception
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* 4 -> enable exception for invalid exception
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* 3 -> enable exception for division by zero exception
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* 2 -> enable exception for overflow exception
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* 1 -> enable exception for underflow exception
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* 0 -> enable exception for inexact exception
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* 20 -> flag invalid exception
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* 19 -> flag division by zero exception
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* 18 -> flag overflow exception
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* 17 -> flag underflow exception
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* 16 -> flag inexact exception
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* 9-8 -> rounding control
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*
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*
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* Rounding Control:
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* 00 - rounding to nearest (RN)
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* 01 - rounding toward zero (RZ)
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* 10 - rounding (up) toward plus infinity (RP)
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* 11 - rounding (down)toward minus infinity (RM)
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*/
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#include <features.h>
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#ifdef __loongarch_soft_float
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#define _FPU_RESERVED 0xffffffff
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#define _FPU_DEFAULT 0x00000000
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typedef unsigned int fpu_control_t;
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#define _FPU_GETCW(cw) (cw) = 0
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#define _FPU_SETCW(cw) (void) (cw)
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extern fpu_control_t __fpu_control;
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#else /* __loongarch_soft_float */
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/* Masks for interrupts. */
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#define _FPU_MASK_V 0x10 /* Invalid operation */
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#define _FPU_MASK_Z 0x08 /* Division by zero */
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#define _FPU_MASK_O 0x04 /* Overflow */
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#define _FPU_MASK_U 0x02 /* Underflow */
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#define _FPU_MASK_I 0x01 /* Inexact operation */
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/* Flush denormalized numbers to zero. */
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#define _FPU_FLUSH_TZ 0x1000000
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/* Rounding control. */
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#define _FPU_RC_NEAREST 0x000 /* RECOMMENDED */
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#define _FPU_RC_ZERO 0x100
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#define _FPU_RC_UP 0x200
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#define _FPU_RC_DOWN 0x300
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/* Mask for rounding control. */
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#define _FPU_RC_MASK 0x300
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#define _FPU_RESERVED 0x0
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#define _FPU_DEFAULT 0x0
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#define _FPU_IEEE 0x1F
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/* Type of the control word. */
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typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
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/* Macros for accessing the hardware control word. */
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extern fpu_control_t __mips_fpu_getcw (void) __THROW;
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extern void __mips_fpu_setcw (fpu_control_t) __THROW;
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#define _FPU_GETCW(cw) __asm__ volatile ("movfcsr2gr %0,$r0" : "=r" (cw))
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#define _FPU_SETCW(cw) __asm__ volatile ("movgr2fcsr $r0,%0" : : "r" (cw))
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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#endif /* __loongarch_soft_float */
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#endif /* fpu_control.h */
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