569 lines
15 KiB
C
569 lines
15 KiB
C
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//#include "ls1c103.h"
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#include "ls1x.h"
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#include "ls1c103_bldc_tim.h"
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#include "ls1c103_bldc_ctrl.h"
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#include "test.h"
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#include "Config.h"
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#include "ls1c103_map.h"
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#include "ls1c103_tim.h"
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#include "ls1x_gpio.h"
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static motor_dir_t direction = MOTOR_FWD;
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static uint32_t dutyfactor = 0;
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static uint32_t is_motor_en = 0;
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static uint32_t bldcm_pulse = 0;
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static void GPIO_Configuration_Bldcm(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* GPIOA Configuration: Channel 1, 2, 3 and 4 as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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/* GPIOA Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_3 | GPIO_Pin_5;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void GPIO_Configuration_Hall(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void GPIO_Configuration_EN(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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AFIO_PORTA &= ~((uint32_t)0x00300000);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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GPIO_SetBits(GPIOA, GPIO_Pin_10);
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}
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static void TIM_MOTOR_CONFIG(){
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uint32_t tmpcr1;
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uint32_t tmpccmrx;
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uint32_t tmpccer;
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uint32_t tmpcr2;
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tmpcr1 = MOTOR_TIM->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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tmpcr1 |= (uint32_t)TIM_CR1_ARPE;
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MOTOR_TIM->CR1 = tmpcr1;
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/* Set the Autoreload value */
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MOTOR_TIM->ARR = (uint32_t)PWM_PERIOD_COUNT - 1;
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/* Set the Prescaler value */
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MOTOR_TIM->PSC = PWM_PRESCALER_COUNT - 1;
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MOTOR_TIM->RCR = 1;
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MOTOR_TIM->EGR = TIM_EGR_UG;
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MOTOR_TIM->CCER &= ~TIM_CCER_CC1E;
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/* Get the TIMx CCER register value */
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tmpccer = MOTOR_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = MOTOR_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = MOTOR_TIM->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC1M;
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tmpccmrx &= ~TIM_CCMR1_CC1S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC1P;
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/* Set the Output Compare Polarity */
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tmpccer |= TIM_OCPolarity_High;
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/* Reset the Output N Polarity level */
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tmpccer &= ~TIM_CCER_CC1NP;
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/* Set the Output N Polarity */
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tmpccer |= TIM_OCNPolarity_High;
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/* Reset the Output N State */
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tmpccer &= ~TIM_CCER_CC1NE;
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/* Reset the Output Compare and Output Compare N IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS1;
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tmpcr2 &= ~TIM_CR2_OIS1N;
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/* Set the Output Idle state */
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tmpcr2 |= TIM_OCIdleState_Reset;
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// /* Set the Output N Idle state */
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tmpcr2 |= TIM_OCNIdleState_Reset;
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/* Write to TIMx CR2 */
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MOTOR_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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MOTOR_TIM->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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MOTOR_TIM->CCR1 = 0;
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/* Write to TIMx CCER */
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MOTOR_TIM->CCER = tmpccer;
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MOTOR_TIM->CCMR1 |= TIM_CCMR1_OC1PE;
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MOTOR_TIM->CCER &= ~TIM_CCER_CC2E;
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/* Get the TIMx CCER register value */
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tmpccer = MOTOR_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = MOTOR_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = MOTOR_TIM->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC2M;
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tmpccmrx &= ~TIM_CCMR1_CC2S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC2P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 4);
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/* Reset the Output N Polarity level */
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tmpccer &= ~TIM_CCER_CC2NP;
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/* Set the Output N Polarity */
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tmpccer |= (TIM_OCNPolarity_High << 4);
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/* Reset the Output N State */
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tmpccer &= ~TIM_CCER_CC2NE;
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/* Reset the Output Compare and Output Compare N IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS2;
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tmpcr2 &= ~TIM_CR2_OIS2N;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 2);
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/* Set the Output N Idle state */
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tmpcr2 |= (TIM_OCNIdleState_Reset << 2);
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/* Write to TIMx CR2 */
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MOTOR_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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MOTOR_TIM->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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MOTOR_TIM->CCR2 = 0;
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/* Write to TIMx CCER */
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MOTOR_TIM->CCER = tmpccer;
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MOTOR_TIM->CCMR1 |= TIM_CCMR1_OC2PE;
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MOTOR_TIM->CCER &= ~TIM_CCER_CC3E;
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/* Get the TIMx CCER register value */
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tmpccer = MOTOR_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = MOTOR_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = MOTOR_TIM->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC3M;
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tmpccmrx &= ~TIM_CCMR2_CC3S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC3P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 8);
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/* Reset the Output N Polarity level */
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tmpccer &= ~TIM_CCER_CC3NP;
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/* Set the Output N Polarity */
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tmpccer |= (TIM_OCNPolarity_High << 8);
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/* Reset the Output N State */
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tmpccer &= ~TIM_CCER_CC3NE;
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/* Reset the Output Compare and Output Compare N IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS3;
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tmpcr2 &= ~TIM_CR2_OIS3N;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 4);
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/* Set the Output N Idle state */
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tmpcr2 |= (TIM_OCNIdleState_Reset << 4);
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/* Write to TIMx CR2 */
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MOTOR_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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MOTOR_TIM->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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MOTOR_TIM->CCR3 = 0;
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/* Write to TIMx CCER */
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MOTOR_TIM->CCER = tmpccer;
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MOTOR_TIM->CCMR2 |= TIM_CCMR2_OC3PE;
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MOTOR_TIM->SMCR &= ~TIM_SMCR_TS;
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MOTOR_TIM->SMCR |= TIM_COM_TS_ITRx;
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/* Select the Capture Compare preload feature */
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MOTOR_TIM->CR2 |= TIM_CR2_CCPC;
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/* Select the Commutation event source */
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MOTOR_TIM->CR2 &= ~TIM_CR2_CCUS;
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/* Disable Commutation Interrupt */
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MOTOR_TIM->DIER &= ~TIM_IT_COM;
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/* Disable Commutation DMA request */
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MOTOR_TIM->DIER &= ~TIM_DMA_COM;
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MOTOR_TIM->CR2 |= TIM_TRGOSource_Update;
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MOTOR_TIM->CCER |= (uint32_t)(TIM_CCER_CC1E);
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MOTOR_TIM->CCER |= (uint32_t)(TIM_CCER_CC2E);
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MOTOR_TIM->CCER |= (uint32_t)(TIM_CCER_CC3E);
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}
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static void TIM_Hall_Init(void)
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{
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uint32_t tmpcr1;
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uint32_t tmpccmr1;
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uint32_t tmpccer;
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/* time base set*/
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tmpcr1 = HALL_TIM->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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tmpcr1 |= (uint32_t)TIM_CR1_ARPE;
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HALL_TIM->CR1 = tmpcr1;
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/* Set the Autoreload value */
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HALL_TIM->ARR = HALL_PERIOD_COUNT - 1;
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/* Set the Prescaler value */
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HALL_TIM->PSC = HALL_PRESCALER_COUNT - 1;
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HALL_TIM->EGR = TIM_EGR_UG;
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//TIM_TI1_SetConfig
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/* Disable the Channel 1: Reset the CC1E Bit */
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HALL_TIM->CCER &= ~TIM_CCER_CC1E;
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tmpccmr1 = HALL_TIM->CCMR1;
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tmpccer = HALL_TIM->CCER;
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/* Select the Input */
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tmpccmr1 &= ~TIM_CCMR1_CC1S;
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tmpccmr1 |= TIM_ICSelection_TRC;
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//tmpccmr1 &= ~TIM_CCMR1_CC2S;
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//tmpccmr1 |= (TIM_ICSelection_DirectTI << 8);
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/* Set the filter */
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tmpccmr1 &= ~TIM_CCMR1_IC1F;
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tmpccmr1 |= ((10 << 4U) & TIM_CCMR1_IC1F); //TIM_ICFilter
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/* Select the Polarity and set the CC1E Bit */
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tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
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//tmpccer |= (TIM_ICPOLARITY_BOTHEDGE & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
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/* Write to TIMx CCMR1 and CCER registers */
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HALL_TIM->CCMR1 = tmpccmr1;
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HALL_TIM->CCER = tmpccer;
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//HALL_TIM->CCMR2 &= ~TIM_CCMR2_CC3S;
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//HALL_TIM->CCMR2 |= TIM_ICSelection_DirectTI;
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/* Reset the IC1PSC Bits */
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HALL_TIM->CCMR1 &= ~TIM_CCMR1_IC1PSC;
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/* Set the IC1PSC value */
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HALL_TIM->CCMR1 |= TIM_ICPSC_DIV1;
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/* Enable the Hall sensor interface (XOR function of the three inputs) */
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HALL_TIM->CR2 |= TIM_CR2_TI1S;
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/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
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HALL_TIM->SMCR &= ~TIM_SMCR_TS;
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HALL_TIM->SMCR |= TIM_TS_TI1F_ED;
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/* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
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HALL_TIM->SMCR &= ~TIM_SMCR_SMS;
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HALL_TIM->SMCR |= TIM_SlaveMode_Reset;
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HALL_TIM->SR &= ~TIM_IT_Update;
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HALL_TIM->SR &= ~TIM_IT_Trigger;
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}
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static void TIM_PID_CONFIG(void)
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{
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uint32_t tmpcr1;
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tmpcr1 = BASIC_TIM->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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tmpcr1 |= TIM_CR1_ARPE;
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BASIC_TIM->CR1 = tmpcr1;
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/* Set the Autoreload value */
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BASIC_TIM->ARR = (uint32_t)BASIC_PERIOD_COUNT ;
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/* Set the Prescaler value */
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BASIC_TIM->PSC = BASIC_PRESCALER_COUNT ;
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BASIC_TIM->EGR = TIM_EGR_UG;
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BASIC_TIM->SR &= (uint32_t)~TIM_IT_Update;
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BASIC_TIM->DIER |= (TIM_IT_Update);
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BASIC_TIM->CR1|=(TIM_CR1_CEN);
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// intc enable
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// INT_EDGE &= 0;
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// INT_EN |= (1<<6);
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}
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void Motor_Init(){
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printf("Motor config begin\n\r");
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GPIO_Configuration_Bldcm();
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GPIO_Configuration_EN();
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TIM_MOTOR_CONFIG();
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printf("Motor config complete\n\r");
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}
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void Hall_Init(void)
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{
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printf("Hall config begin\n\r");
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GPIO_Configuration_Hall();
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TIM_Hall_Init();
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printf("Hall config complete\n\r");
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}
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void BasicTim_Init(){
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printf("Basic config begin\n\r");
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TIM_PID_CONFIG();
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printf("Basic config complete\n\r");
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}
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void set_pwm_pulse(uint32_t pulse)
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{
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bldcm_pulse = pulse;
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}
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void set_direction(motor_dir_t dir)
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{
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direction = dir;
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||
|
|
}
|
||
|
|
|
||
|
|
void stop_pwm_output(void)
|
||
|
|
{
|
||
|
|
MOTOR_TIM->BDTR &= ~(TIM_BDTR_MOE);
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
MOTOR_TIM->EGR = TIM_EventSource_COM;
|
||
|
|
}
|
||
|
|
|
||
|
|
void hall_enable(void)
|
||
|
|
{
|
||
|
|
HALL_TIM->DIER |= TIM_IT_Trigger;
|
||
|
|
HALL_TIM->DIER |= TIM_IT_Update;
|
||
|
|
HALL_TIM->CCER |= TIM_CCER_CC1E;
|
||
|
|
HALL_TIM->CR1 |= TIM_CR1_CEN;
|
||
|
|
HALL_TriggerCallback();
|
||
|
|
}
|
||
|
|
|
||
|
|
void hall_disable(void)
|
||
|
|
{
|
||
|
|
HALL_TIM->DIER &= ~TIM_IT_Trigger;
|
||
|
|
HALL_TIM->DIER &= ~TIM_IT_Update;
|
||
|
|
HALL_TIM->CCER &= ~TIM_CCER_CC1E;
|
||
|
|
HALL_TIM->CR1 &= ~TIM_CR1_CEN;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint8_t get_hall_state(void)
|
||
|
|
{
|
||
|
|
uint8_t state = 0;
|
||
|
|
uint8_t hallu, hallv, hallw;
|
||
|
|
/* get hall status U */
|
||
|
|
hallu = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_7);
|
||
|
|
if(hallu==1)
|
||
|
|
{
|
||
|
|
state |= 0x01U << 0;
|
||
|
|
}
|
||
|
|
/* get hall status V */
|
||
|
|
hallv = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_8);
|
||
|
|
if(hallv==1)
|
||
|
|
{
|
||
|
|
state |= 0x01U << 1;
|
||
|
|
}
|
||
|
|
/* get hall status W */
|
||
|
|
hallw = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9);
|
||
|
|
if(hallw==1)
|
||
|
|
{
|
||
|
|
state |= 0x01U << 2;
|
||
|
|
}
|
||
|
|
return state; // return HALL status
|
||
|
|
}
|
||
|
|
|
||
|
|
int update = 0; // hall timer update flag,to watch timeout event
|
||
|
|
|
||
|
|
|
||
|
|
void HALL_TriggerCallback(void)
|
||
|
|
{
|
||
|
|
/* get hall sensor status */
|
||
|
|
uint8_t step = 0;
|
||
|
|
step = get_hall_state();
|
||
|
|
//printf("%d\n\r",step);
|
||
|
|
if(direction == MOTOR_FWD)
|
||
|
|
{
|
||
|
|
switch(step)
|
||
|
|
{
|
||
|
|
case 1: /* U+ W- */
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 2: /* V+ U- */
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 3: /* V+ W- */
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 4: /* W+ V- */
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 5: /* U+ V -*/
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 6: /* W+ U- */
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
switch(step)
|
||
|
|
{
|
||
|
|
case 1: /* W+ U- */
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC1NE;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 2: /* U+ V -*/
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC2NE;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 3: /* W+ V- */
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 4: /* V+ W- */
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC3NE;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 5: /* V+ U- */
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC3NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR2 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC1NE;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 6: /* U+ W- */
|
||
|
|
MOTOR_TIM->CCR2 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC2NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR3 = 0;
|
||
|
|
MOTOR_TIM->CCER &= ~TIM_CCER_CC1NE;
|
||
|
|
|
||
|
|
MOTOR_TIM->CCR1 = bldcm_pulse;
|
||
|
|
MOTOR_TIM->CCER |= TIM_CCER_CC3NE;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
//soft COM event
|
||
|
|
MOTOR_TIM->EGR = TIM_EventSource_COM;
|
||
|
|
update = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void HALL_PeriodElapsedCallback(void)
|
||
|
|
{
|
||
|
|
if (update++ > 1) // time out
|
||
|
|
{
|
||
|
|
printf("TIMEOUT,MOTOR STOP!!!\n\r");
|
||
|
|
update = 0;
|
||
|
|
|
||
|
|
/* stop PWM output */
|
||
|
|
hall_disable(); // disable Hall
|
||
|
|
stop_pwm_output();
|
||
|
|
BLDCM_DISABLE_EN();
|
||
|
|
}
|
||
|
|
}
|