195 lines
6.6 KiB
C
195 lines
6.6 KiB
C
//#include "ls1c103.h"
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#include "ls1x.h"
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#include "test.h"
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#include "Config.h"
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#include "ls1c103_dma.h"
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#include "ls1c103_map.h"
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static int err;
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#define DMA_TEST_ADDR0 (RAM0_BASE + 0x400)
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#define DMA_TEST_ADDR1 (RAM0_BASE + 0x500)
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#define DMA_TEST_ADDR2 (RAM1_BASE + 0x400)
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#define BufferSize 32
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typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
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ucint32_t SRC_Const_Buffer[BufferSize]= {0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
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0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
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0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
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0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
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0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
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0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
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0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
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0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
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//Test Case by Loongson
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TestStatus Buffercmp(ucint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength)
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{
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while(BufferLength--)
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{
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if(*pBuffer != *pBuffer1)
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{
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return FAILED;
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}
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pBuffer++;
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pBuffer1++;
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}
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return PASSED;
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}
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static void dma_ch1_cfg()
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_DeInit(DMA1_Channel1);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer;
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DMA_TEST_ADDR0;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = BufferSize;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
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DMA_Init(DMA1_Channel1, &DMA_InitStructure);
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}
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static void dma_ch2_cfg()
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_DeInit(DMA1_Channel2);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DMA_TEST_ADDR0;
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DMA_TEST_ADDR1;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = BufferSize;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
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DMA_Init(DMA1_Channel2, &DMA_InitStructure);
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}
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static void dma_ch3_cfg()
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_DeInit(DMA1_Channel3);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DMA_TEST_ADDR1;
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DMA_TEST_ADDR2;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = BufferSize;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
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DMA_Init(DMA1_Channel3, &DMA_InitStructure);
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}
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static void dma_ch4_cfg()
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_DeInit(DMA1_Channel4);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DMA_TEST_ADDR2;
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DMA_TEST_ADDR0;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = BufferSize;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
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DMA_Init(DMA1_Channel4, &DMA_InitStructure);
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}
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static int dma_test(void)
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{
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uint32_t tcif1, tcif2, tcif3, tcif4;
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TestStatus TransferStatus;
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dma_ch1_cfg();
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dma_ch2_cfg();
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dma_ch3_cfg();
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dma_ch4_cfg();
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printf("CH CFG DONE\n");
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//DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE);
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DMA_Cmd(DMA1_Channel1, ENABLE);
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tcif1 = DMA_GetFlagStatus(DMA1_FLAG_TC1);
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while (tcif1==0)
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{
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tcif1 = DMA_GetFlagStatus(DMA1_FLAG_TC1);
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}
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printf("tcif1:%d\n", tcif1);
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TransferStatus = Buffercmp(SRC_Const_Buffer,(uint32_t *)DMA_TEST_ADDR0, BufferSize); //Check Transfer by CPU access
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if (TransferStatus == FAILED) return 1;
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else printf("CH1 Verified\n");
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DMA_DeInit(DMA1_Channel1);
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DMA_ClearFlag(DMA1_FLAG_GL1);
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DMA_Cmd(DMA1_Channel2, ENABLE); //Transfer ch2 with 0x400 = DST; Prio_lvl = M
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tcif2 = DMA_GetFlagStatus(DMA1_FLAG_TC2);
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while (tcif2==0)
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{
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tcif2 = DMA_GetFlagStatus(DMA1_FLAG_TC2);
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}
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TransferStatus = Buffercmp((uint32_t *)DMA_TEST_ADDR1, (uint32_t *)DMA_TEST_ADDR0, BufferSize);
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if (TransferStatus == FAILED) return 1;
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else printf("CH2 Verified\n");
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DMA_DeInit(DMA1_Channel2);
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DMA_ClearFlag(DMA1_FLAG_GL2);
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DMA_Cmd(DMA1_Channel3, ENABLE); //Transfer ch3 with 0x500 = SRC; Prio_lvl = H
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tcif3 = DMA_GetFlagStatus(DMA1_FLAG_TC3);
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while (tcif3==0)
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{
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tcif3 = DMA_GetFlagStatus(DMA1_FLAG_TC3);
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}
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TransferStatus = Buffercmp((uint32_t *)DMA_TEST_ADDR2,(uint32_t *) DMA_TEST_ADDR1, BufferSize);
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if (TransferStatus == FAILED) return 1;
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else printf("CH3 Verified\n");
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DMA_ClearFlag(DMA1_FLAG_GL3);
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DMA_DeInit(DMA1_Channel3);
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DMA_Cmd(DMA1_Channel4, ENABLE); //Transfer ch4 with 0x600 = DST; Prio_lvl = V
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tcif4 = DMA_GetFlagStatus(DMA1_FLAG_TC4);
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while (tcif4==0)
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{
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tcif4 = DMA_GetFlagStatus(DMA1_FLAG_TC4);
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}
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TransferStatus = Buffercmp((uint32_t *)DMA_TEST_ADDR0,(uint32_t *) DMA_TEST_ADDR2, BufferSize);
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if (TransferStatus == FAILED) return 1;
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else printf("CH4 Verified\n");
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DMA_ClearFlag(DMA1_FLAG_GL4);
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DMA_DeInit(DMA1_Channel4);
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return 0;
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}
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int dma_ram(int argc, void *argv[])
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{
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dma_test();
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return 0;
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}
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