662 lines
31 KiB
C
662 lines
31 KiB
C
/* Includes ------------------------------------------------------------------*/
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#include "ls1c103_dma.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* DMA ENABLE mask */
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#define CCR_ENABLE_Set ((uint32_t)0x00000001)
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#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
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/* DMA1 Channelx interrupt pending bit masks */
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#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
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#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
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#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
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#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
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#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
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#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
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#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
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/* DMA2 Channelx interrupt pending bit masks */
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#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)
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#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)
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#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)
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#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)
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#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)
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/* DMA2 FLAG mask */
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#define FLAG_Mask ((uint32_t)0x10000000)
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/* DMA registers Masks */
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#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/*******************************************************************************
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* Function Name : DMA_DeInit
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* Description : Deinitializes the DMAy Channelx registers to their default reset
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* values.
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* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
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* DMA Channel.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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/* Disable the selected DMAy Channelx */
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DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
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/* Reset DMAy Channelx control register */
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DMAy_Channelx->CCR = 0;
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/* Reset DMAy Channelx remaining bytes register */
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DMAy_Channelx->CNDTR = 0;
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/* Reset DMAy Channelx peripheral address register */
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DMAy_Channelx->CPAR = 0;
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/* Reset DMAy Channelx memory address register */
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DMAy_Channelx->CMAR = 0;
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switch (*(uint32_t*)&DMAy_Channelx)
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{
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case DMA1_Channel1_BASE:
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/* Reset interrupt pending bits for DMA1 Channel1 */
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DMA1->IFCR |= DMA1_Channel1_IT_Mask;
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break;
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case DMA1_Channel2_BASE:
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/* Reset interrupt pending bits for DMA1 Channel2 */
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DMA1->IFCR |= DMA1_Channel2_IT_Mask;
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break;
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case DMA1_Channel3_BASE:
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/* Reset interrupt pending bits for DMA1 Channel3 */
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DMA1->IFCR |= DMA1_Channel3_IT_Mask;
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break;
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case DMA1_Channel4_BASE:
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/* Reset interrupt pending bits for DMA1 Channel4 */
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DMA1->IFCR |= DMA1_Channel4_IT_Mask;
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break;
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case DMA1_Channel5_BASE:
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/* Reset interrupt pending bits for DMA1 Channel5 */
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DMA1->IFCR |= DMA1_Channel5_IT_Mask;
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break;
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case DMA1_Channel6_BASE:
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/* Reset interrupt pending bits for DMA1 Channel6 */
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DMA1->IFCR |= DMA1_Channel6_IT_Mask;
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break;
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case DMA1_Channel7_BASE:
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/* Reset interrupt pending bits for DMA1 Channel7 */
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DMA1->IFCR |= DMA1_Channel7_IT_Mask;
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break;
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case DMA2_Channel1_BASE:
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/* Reset interrupt pending bits for DMA2 Channel1 */
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DMA2->IFCR |= DMA2_Channel1_IT_Mask;
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break;
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case DMA2_Channel2_BASE:
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/* Reset interrupt pending bits for DMA2 Channel2 */
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DMA2->IFCR |= DMA2_Channel2_IT_Mask;
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break;
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case DMA2_Channel3_BASE:
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/* Reset interrupt pending bits for DMA2 Channel3 */
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DMA2->IFCR |= DMA2_Channel3_IT_Mask;
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break;
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case DMA2_Channel4_BASE:
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/* Reset interrupt pending bits for DMA2 Channel4 */
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DMA2->IFCR |= DMA2_Channel4_IT_Mask;
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break;
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case DMA2_Channel5_BASE:
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/* Reset interrupt pending bits for DMA2 Channel5 */
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DMA2->IFCR |= DMA2_Channel5_IT_Mask;
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break;
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default:
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break;
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}
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}
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/*******************************************************************************
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* Function Name : DMA_Init
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* Description : Initializes the DMAy Channelx according to the specified
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* parameters in the DMA_InitStruct.
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* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
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* DMA Channel.
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* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
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* contains the configuration information for the specified
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* DMA Channel.
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* Output : None
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* Return : None
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******************************************************************************/
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void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
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assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
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assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
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assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
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assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
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assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
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assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
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assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
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assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
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/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
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/* Get the DMAy_Channelx CCR value */
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tmpreg = DMAy_Channelx->CCR;
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/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
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tmpreg &= CCR_CLEAR_Mask;
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/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
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/* Set DIR bit according to DMA_DIR value */
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/* Set CIRC bit according to DMA_Mode value */
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/* Set PINC bit according to DMA_PeripheralInc value */
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/* Set MINC bit according to DMA_MemoryInc value */
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/* Set PSIZE bits according to DMA_PeripheralDataSize value */
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/* Set MSIZE bits according to DMA_MemoryDataSize value */
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/* Set PL bits according to DMA_Priority value */
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/* Set the MEM2MEM bit according to DMA_M2M value */
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tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
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DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
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DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
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DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
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/* Write to DMAy Channelx CCR */
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DMAy_Channelx->CCR = tmpreg;
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/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
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/* Write to DMAy Channelx CNDTR */
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DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
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/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
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/* Write to DMAy Channelx CPAR */
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DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
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/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
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/* Write to DMAy Channelx CMAR */
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DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
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}
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/*******************************************************************************
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* Function Name : DMA_StructInit
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* Description : Fills each DMA_InitStruct member with its default value.
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* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
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* which will be initialized.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
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{
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/*-------------- Reset DMA init structure parameters values ------------------*/
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/* Initialize the DMA_PeripheralBaseAddr member */
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DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
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/* Initialize the DMA_MemoryBaseAddr member */
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DMA_InitStruct->DMA_MemoryBaseAddr = 0;
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/* Initialize the DMA_DIR member */
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DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
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/* Initialize the DMA_BufferSize member */
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DMA_InitStruct->DMA_BufferSize = 0;
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/* Initialize the DMA_PeripheralInc member */
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DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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/* Initialize the DMA_MemoryInc member */
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DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
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/* Initialize the DMA_PeripheralDataSize member */
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DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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/* Initialize the DMA_MemoryDataSize member */
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DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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/* Initialize the DMA_Mode member */
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DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
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/* Initialize the DMA_Priority member */
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DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
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/* Initialize the DMA_M2M member */
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DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
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}
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/*******************************************************************************
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* Function Name : DMA_Cmd
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* Description : Enables or disables the specified DMAy Channelx.
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* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
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* DMA Channel.
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* - NewState: new state of the DMAy Channelx.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
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{
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// /* Check the parameters */
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// assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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// assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected DMAy Channelx */
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DMAy_Channelx->CCR |= CCR_ENABLE_Set;
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}
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else
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{
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/* Disable the selected DMAy Channelx */
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DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
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}
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}
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/*******************************************************************************
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* Function Name : DMA_ITConfig
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* Description : Enables or disables the specified DMAy Channelx interrupts.
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* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
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* DMA Channel.
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* - DMA_IT: specifies the DMA interrupts sources to be enabled
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* or disabled.
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* This parameter can be any combination of the following values:
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* - DMA_IT_TC: Transfer complete interrupt mask
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* - DMA_IT_HT: Half transfer interrupt mask
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* - DMA_IT_TE: Transfer error interrupt mask
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* - NewState: new state of the specified DMA interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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assert_param(IS_DMA_CONFIG_IT(DMA_IT));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected DMA interrupts */
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DMAy_Channelx->CCR |= DMA_IT;
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}
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else
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{
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/* Disable the selected DMA interrupts */
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DMAy_Channelx->CCR &= ~DMA_IT;
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}
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}
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/*******************************************************************************
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* Function Name : DMA_GetCurrDataCounter
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* Description : Returns the number of remaining data units in the current
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* DMAy Channelx transfer.
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* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
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* DMA Channel.
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* Output : None
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* Return : The number of remaining data units in the current DMAy Channelx
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* transfer.
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*******************************************************************************/
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uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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/* Return the number of remaining data units for DMAy Channelx */
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return ((uint16_t)(DMAy_Channelx->CNDTR));
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}
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/*******************************************************************************
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* Function Name : DMA_GetFlagStatus
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* Description : Checks whether the specified DMAy Channelx flag is set or not.
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* Input : - DMA_FLAG: specifies the flag to check.
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* This parameter can be one of the following values:
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* - DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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* - DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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* - DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
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* - DMA1_FLAG_GL4: DMA1 Channel4 global flag.
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* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
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* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
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* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
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* - DMA1_FLAG_GL5: DMA1 Channel5 global flag.
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* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
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* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
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* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
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* - DMA1_FLAG_GL6: DMA1 Channel6 global flag.
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* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
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* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
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* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
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* - DMA1_FLAG_GL7: DMA1 Channel7 global flag.
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* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
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* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
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* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
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* - DMA2_FLAG_GL1: DMA2 Channel1 global flag.
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* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
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* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
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* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
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* - DMA2_FLAG_GL2: DMA2 Channel2 global flag.
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* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
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* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
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* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
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* - DMA2_FLAG_GL3: DMA2 Channel3 global flag.
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* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
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* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
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* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
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* - DMA2_FLAG_GL4: DMA2 Channel4 global flag.
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* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
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* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
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* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
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* - DMA2_FLAG_GL5: DMA2 Channel5 global flag.
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* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
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* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
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* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
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* Output : None
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* Return : The new state of DMA_FLAG (SET or RESET).
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*******************************************************************************/
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FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
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{
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FlagStatus bitstatus = RESET;
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
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/* Calculate the used DMA */
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if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
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{
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/* Get DMA2 ISR register value */
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tmpreg = DMA2->ISR ;
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}
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else
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{
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/* Get DMA1 ISR register value */
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tmpreg = DMA1->ISR ;
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}
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/* Check the status of the specified DMA flag */
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if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
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{
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/* DMA_FLAG is set */
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bitstatus = SET;
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}
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else
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{
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/* DMA_FLAG is reset */
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bitstatus = RESET;
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}
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/* Return the DMA_FLAG status */
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return bitstatus;
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}
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/*******************************************************************************
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* Function Name : DMA_ClearFlag
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* Description : Clears the DMAy Channelx's pending flags.
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* Input : - DMA_FLAG: specifies the flag to clear.
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* This parameter can be any combination (for the same DMA) of
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* the following values:
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* - DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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* - DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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* - DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
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* - DMA1_FLAG_GL4: DMA1 Channel4 global flag.
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* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
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* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
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* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
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* - DMA1_FLAG_GL5: DMA1 Channel5 global flag.
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* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
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* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
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* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
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* - DMA1_FLAG_GL6: DMA1 Channel6 global flag.
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* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
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* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
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* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||
* - DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||
* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||
* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||
* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||
* - DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||
* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||
* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||
* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||
* - DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||
* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||
* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||
* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||
* - DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||
* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||
* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||
* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||
* - DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||
* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||
* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||
* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||
* - DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||
* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||
* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||
* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||
* Output : None
|
||
* Return : None
|
||
*******************************************************************************/
|
||
void DMA_ClearFlag(uint32_t DMA_FLAG)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
|
||
|
||
/* Calculate the used DMA */
|
||
if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||
{
|
||
/* Clear the selected DMA flags */
|
||
DMA2->IFCR = DMA_FLAG;
|
||
}
|
||
else
|
||
{
|
||
/* Clear the selected DMA flags */
|
||
DMA1->IFCR = DMA_FLAG;
|
||
}
|
||
}
|
||
|
||
/*******************************************************************************
|
||
* Function Name : DMA_GetITStatus
|
||
* Description : Checks whether the specified DMAy Channelx interrupt has
|
||
* occurred or not.
|
||
* Input : - DMA_IT: specifies the DMA interrupt source to check.
|
||
* This parameter can be one of the following values:
|
||
* - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||
* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||
* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||
* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||
* - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||
* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||
* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||
* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||
* - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||
* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||
* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||
* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||
* - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||
* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||
* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||
* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||
* - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||
* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||
* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||
* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||
* - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||
* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||
* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||
* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||
* - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||
* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||
* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||
* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||
* - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||
* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||
* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||
* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||
* - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||
* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||
* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||
* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||
* - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||
* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||
* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||
* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||
* - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||
* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||
* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||
* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||
* - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||
* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||
* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||
* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||
* Output : None
|
||
* Return : The new state of DMA_IT (SET or RESET).
|
||
*******************************************************************************/
|
||
ITStatus DMA_GetITStatus(uint32_t DMA_IT)
|
||
{
|
||
ITStatus bitstatus = RESET;
|
||
uint32_t tmpreg = 0;
|
||
|
||
/* Check the parameters */
|
||
assert_param(IS_DMA_GET_IT(DMA_IT));
|
||
|
||
/* Calculate the used DMA */
|
||
if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
|
||
{
|
||
/* Get DMA2 ISR register value */
|
||
tmpreg = DMA2->ISR ;
|
||
}
|
||
else
|
||
{
|
||
/* Get DMA1 ISR register value */
|
||
tmpreg = DMA1->ISR ;
|
||
}
|
||
|
||
/* Check the status of the specified DMA interrupt */
|
||
if ((tmpreg & DMA_IT) != (uint32_t)RESET)
|
||
{
|
||
/* DMA_IT is set */
|
||
bitstatus = SET;
|
||
}
|
||
else
|
||
{
|
||
/* DMA_IT is reset */
|
||
bitstatus = RESET;
|
||
}
|
||
/* Return the DMA_IT status */
|
||
return bitstatus;
|
||
}
|
||
|
||
/*******************************************************************************
|
||
* Function Name : DMA_ClearITPendingBit
|
||
* Description : Clears the DMAy Channelx<6C>s interrupt pending bits.
|
||
* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
|
||
* This parameter can be any combination (for the same DMA) of
|
||
* the following values:
|
||
* - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||
* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||
* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||
* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||
* - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||
* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||
* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||
* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||
* - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||
* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||
* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||
* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||
* - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||
* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||
* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||
* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||
* - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||
* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||
* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||
* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||
* - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||
* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||
* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||
* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||
* - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||
* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||
* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||
* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||
* - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||
* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||
* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||
* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||
* - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||
* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||
* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||
* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||
* - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||
* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||
* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||
* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||
* - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||
* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||
* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||
* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||
* - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||
* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||
* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||
* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||
* Output : None
|
||
* Return : None
|
||
*******************************************************************************/
|
||
void DMA_ClearITPendingBit(uint32_t DMA_IT)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_DMA_CLEAR_IT(DMA_IT));
|
||
|
||
/* Calculate the used DMA */
|
||
if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
|
||
{
|
||
/* Clear the selected DMA interrupt pending bits */
|
||
DMA2->IFCR = DMA_IT;
|
||
}
|
||
else
|
||
{
|
||
/* Clear the selected DMA interrupt pending bits */
|
||
DMA1->IFCR = DMA_IT;
|
||
}
|
||
}
|
||
|
||
|