104 lines
1.9 KiB
C
104 lines
1.9 KiB
C
#include "ls1c103_pmu.h"
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#include "ls1x.h"
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#include "Config.h"
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extern void cpu_wait(void);
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uint32_t pmu_get_time()
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{
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uint32_t r;
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read_reg32(r, PMU_BASE, PMU_Count);
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return r;
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}
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void pmu_wake_timer_start(uint32_t delta)
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{
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uint32_t r;
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read_reg32(r, PMU_BASE, PMU_Count);
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r += delta;
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write_reg32(r, PMU_BASE, PMU_Compare);
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read_reg32(r, PMU_BASE, PMU_Command);
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r |= 0x1 << 8;
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write_reg32(r, PMU_BASE, PMU_Command);
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}
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void pmu_wake_timer_stop()
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{
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uint32_t r;
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read_reg32(r, PMU_BASE, PMU_Command);
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r &= ~(0x1 << 8);// clear enable bit will also clear the recorded intr state
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write_reg32(r, PMU_BASE, PMU_Command);
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}
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void pmu_watchdog_feed()
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{
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uint32_t r = 0xa55a55aa;
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write_reg32(r, PMU_BASE, PMU_WdtFeed);
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}
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void pmu_watchdog_set(uint32_t delay)
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{
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uint32_t r = ((~delay) << 16 ) | delay;
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write_reg32(r, PMU_BASE, PMU_WdtCfg);
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}
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uint32_t wait_int()
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{
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//if (cfg_waitop_sleep) cpu_sleep();
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//else
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printf("idle 0\n");
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cpu_wait();
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printf("int trig\n");
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// uint32_t intr = pmu_intr;
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// pmu_intr = 0;
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// return intr;
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return 0;
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}
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uint32_t wait_cpu_int()
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{
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cpu_wait();
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// uint32_t intr = cpu_intr;
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// cpu_intr = 0;
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// return intr;
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return 0;
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}
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void pmu_rst_cmd(uint32_t PMU_RstArr, uint32_t NewState)
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{
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if (NewState != DISABLE)
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{
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PMU_SOFTRST |= PMU_RstArr;
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}
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else
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{
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PMU_SOFTRST &= ~PMU_RstArr;
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}
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}
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void pmu_clk_cmd(uint32_t PMU_ClkArr, uint32_t NewState)
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{
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if (NewState != DISABLE)
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{
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PMU_CLKOFF |= PMU_ClkArr;
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}
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else
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{
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PMU_CLKOFF &= ~PMU_ClkArr;
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}
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}
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/*
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void pmu_gpio_bit_write(int idx, uint32_t flag)
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{
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write_reg8_v(flag, idx, (GPIOA_REG_BASE+PMU_GPIOBit));
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}
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uint32_t pmu_gpio_bit_read(int idx)
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{
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uint32_t r;
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read_reg8_v(r, idx, (GPIOA_REG_BASE+PMU_GPIOBit));
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return r;
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}
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*/
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