206 lines
6.9 KiB
C
206 lines
6.9 KiB
C
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#ifndef _START_H_
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#define _START_H_
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/****************** CLK CONFIG ******************/
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#if defined (LS1C102)
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#define BSS_BASE (0x80000000)
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#define DATA_BASE (0x80001000)
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#define SP_BASE (0x80002000-132)
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#define REGS_MEM (0x80002000) //first use in REGS_MEM-4
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#define CACHE_OP (0xfff1ffff)
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#define ADDR_MAP (0x76503210)
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#define INT_VECTOR (0xbbc)
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#define INTC_VECTOR (0x40)
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#elif defined (LS1C103) /*ls1c103 define*/
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#define BSS_BASE (0x10000000)
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#define DATA_BASE (0x10001000)
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#define SP_BASE (0x10002000-132)
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#define REGS_MEM (0x10002000) //first use in REGS_MEM-4
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#define CACHE_OP (0xfffffff1)
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#define ADDR_MAP (0x76043210)
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#define INT_VECTOR (0x8dc)
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#define INTC_VECTOR (0x20)
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#endif
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// for func-test purpose
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#define WATCHDOG_ON_DEMAND 0x12344321
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#define NMI_ON_DEMAND 0x43211234
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#if defined(LS1C102)
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#define UNCACHED_MEMORY_ADDR 0xa0000000
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#define UNCACHED_TO_PHYS(x) ((x) & 0x1fffffff)
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#define PHYS_TO_UNCACHED(x) ((x) | UNCACHED_MEMORY_ADDR)
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#define RAM0_BASE PHYS_TO_UNCACHED(0x00000000) //iram
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#define RAM1_BASE PHYS_TO_UNCACHED(0x00001000) //dram
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#define SPI_MEM_BASE PHYS_TO_UNCACHED(0x1e000000) //spi_flash
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#define FLASH_MEM_BASE PHYS_TO_UNCACHED(0x1f000000) //on-chip flash
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#define FLASH_BASE PHYS_TO_UNCACHED(0x1fe60000) //flash regs
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#define SPI_BASE PHYS_TO_UNCACHED(0x1fe70000) //spi regs
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#define UART0_BASEADDR PHYS_TO_UNCACHED(0x1fe80000) //uart0
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#define UART1_BASEADDR PHYS_TO_UNCACHED(0x1fe88000) //uart1
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#define UART2_BASEADDR PHYS_TO_UNCACHED(0x1fe8c000) //uart2
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#define I2C_BASE PHYS_TO_UNCACHED(0x1fe90000) //i2c
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#define INTC_BASE PHYS_TO_UNCACHED(0x1fea0000) //Interrupt_Regs_Baseadd
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#define PMU_BASE PHYS_TO_UNCACHED(0x1feb0000) //PMU
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#define TSENSOR_BASE PHYS_TO_UNCACHED(0x1feb4000) //tsensor
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#define RTC_BASE PHYS_TO_UNCACHED(0x1feb8000) //rtc
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#define DMA_BASE PHYS_TO_UNCACHED(0x1fec0000) //DMA
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#define VPWM_BASE PHYS_TO_UNCACHED(0x1fec0020) //vpwm
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#define TIMER_BASE PHYS_TO_UNCACHED(0x1fed0000) //timer
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#define UART_BASEADDR UART0_BASEADDR
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//#define UART_BASEADDR UART1_BASEADDR
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#elif defined(LS1C103)
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#define UNCACHED_MEMORY_ADDR 0x00000000
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#define PHYS_TO_UNCACHED(x) ((x) | UNCACHED_MEMORY_ADDR)
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#define RAM0_BASE 0x10000000
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#define RAM1_BASE 0x10001000
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#define SPI_MEM_BASE 0x20000000
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#define FLASH_MEM_BASE 0x18000000
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#define ATIM_BASE PHYS_TO_UNCACHED(0x00001000)
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#define GTIM_BASE PHYS_TO_UNCACHED(0x00002000)
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#define BTIM_BASE PHYS_TO_UNCACHED(0x00003000)
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#define ADC_BASE PHYS_TO_UNCACHED(0x00004000)
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#define DMA_BASE PHYS_TO_UNCACHED(0x00005000)
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#define CRC_BASE PHYS_TO_UNCACHED(0x00006000)
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#define FLASH_BASE PHYS_TO_UNCACHED(0x00007000)
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#define SPI_BASE PHYS_TO_UNCACHED(0x00008000)
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#define UART0_BASEADDR PHYS_TO_UNCACHED(0x00009000)
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#define UART1_BASEADDR PHYS_TO_UNCACHED(0x00009100)
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#define I2C_BASE PHYS_TO_UNCACHED(0x0000a000)
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#define INTC_BASE PHYS_TO_UNCACHED(0x0000b000)
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#define PMU_BASE PHYS_TO_UNCACHED(0x0000c000)
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#define RTC_BASE PHYS_TO_UNCACHED(0x0000c800)
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#define IOCFG_BASE PHYS_TO_UNCACHED(0x0000d000)
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#define UART_BASEADDR UART0_BASEADDR
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//#define UART_BASEADDR UART1_BASEADDR
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#endif
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#if defined(LS1C102)
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#define PMU_ChipCtrl 0x00
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#define PMU_Command 0x04
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#define PMU_Count 0x08
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#define PMU_Compare 0x0c
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#define PMU_WdtCfg 0x30
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#define PMU_WdtFeed 0x34
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#define PMU_PowerCfg 0x38
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#define PMU_CommandW 0x3c
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#define PMU_GPIOAOE_OFFSET 0x40
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#define PMU_GPIOAO_OFFSET 0x44
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#define PMU_GPIOAI_OFFSET 0x48
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#define PMU_GPIOBOE_OFFSET 0x50
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#define PMU_GPIOBO_OFFSET 0x54
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#define PMU_GPIOBI_OFFSET 0x58
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#define PMU_PULSE0_OFFSET 0x60
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#define PMU_PULSE1_OFFSET 0x64
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#define PMU_ADCCTRL_OFFSET 0x6c
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#define PMU_ADCDAT_OFFSET 0x70
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//PMU access by 8-bit
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#define PMU_GPIOBIT_OFFSET 0x80
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#define PMU_SoftRst 0x10
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#define PMU_ClkOff 0x14
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#define PMU_SrProt 0x18
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#define PMU_UserDat1 0x64
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#define PMU_UserDat2 0x68
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#define PMU_UserDat3 0x6c
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#define ResetSrc (26)
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#define PMU_UserDat0 0x68
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#define AFIO_Sela 0x10
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#define AFIO_Selb 0x14
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#define AFIO_Selc 0x18
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#define AFIO_Seld 0x1c
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#define EXTI_En 0x20
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#define EXTI_Pol 0x24
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#define EXTI_Edge 0x28
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#define EXTI_Src 0x2c
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#define AFIO_BASE (PMU_BASE + 0x10)
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#define GPIOA_BASE (PMU_BASE + 0x40)
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#define GPIOB_BASE (PMU_BASE + 0x50)
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#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
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#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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#elif defined(LS1C103)/********LS1C103**********/
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#define PMU_ChipCtrl 0x00
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#define PMU_Command 0x04
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#define PMU_Count 0x08
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#define PMU_Compare 0x0c
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#define PMU_WdtCfg 0x30
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#define PMU_WdtFeed 0x34
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#define PMU_PowerCfg 0x38
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#define PMU_CommandW 0x3c
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#define PMU_GPIOAOE_OFFSET 0x40
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#define PMU_GPIOAO_OFFSET 0x44
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#define PMU_GPIOAI_OFFSET 0x48
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#define PMU_GPIOBOE_OFFSET 0x50
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#define PMU_GPIOBO_OFFSET 0x54
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#define PMU_GPIOBI_OFFSET 0x58
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#define PMU_PULSE0_OFFSET 0x60
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#define PMU_PULSE1_OFFSET 0x64
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#define PMU_ADCCTRL_OFFSET 0x6c
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#define PMU_ADCDAT_OFFSET 0x70
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//PMU access by 8-bit
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#define PMU_GPIOBIT_OFFSET 0x80
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#define PMU_SoftRst 0x10
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#define PMU_ClkOff 0x14
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#define PMU_SrProt 0x18
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#define PMU_UserDat1 0x64
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#define PMU_UserDat2 0x68
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#define PMU_UserDat3 0x6c
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#define ResetSrc (26)
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#define PMU_UserDat0 0x60
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#define AFIO_REG_BASE (IOCFG_BASE + 0x00000000)
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#define EXTI_REG_BASE (IOCFG_BASE + 0x00000100)
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#define GPIOA_REG_BASE (IOCFG_BASE + 0x00000200)
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#define GPIOB_REG_BASE (IOCFG_BASE + 0x00000300)
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#define AFIO_Sela 0x00
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#define AFIO_Selb 0x04
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#endif
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#if defined(LS1C102)
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#define INTC_EN_OFFSET 0x0
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#define INTC_EDGE_OFFSET 0x1
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#define INTC_POL_OFFSET 0x2
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#define INTC_CLR_OFFSET 0x3
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#define INTC_SET_OFFSET 0x4
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#define INTC_OUT_OFFSET 0x5
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#define INTC_SRPROT_OFFSET 0x6
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#define INTC_CKGATE_OFFSET 0x7
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#elif defined(LS1C103)
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#endif
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#endif /* _START_H_ */
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