521 lines
15 KiB
C
521 lines
15 KiB
C
//#include "ls1c103.h"
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#include "ls1x.h"
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#include "ls1x_gpio.h"
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#include "test.h"
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#include "Config.h"
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#include "ls1x_gpio.h"
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#include "ls1c103_map.h"
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#include "ls1c103_tim.h"
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static int err;
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#define KEY0 (0x00)
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#define KEY1 (0x01)
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#define STEER_TIM TIM1
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#define STEER_TIM2 TIM2
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#define STEER_PERIOD_COUNT (10158)
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#define STEER_PRESCALER_COUNT (21)
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extern INT8U x_getchar(void);
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extern unsigned int str2num(unsigned char *);
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static uint8_t scan_key(uint32_t key){
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uint16_t keyuse;
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if(key == KEY1){
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keyuse = GPIO_Pin_13;
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}
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else{
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keyuse = GPIO_Pin_12;
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}
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uint8_t sflag = GPIO_ReadInputDataBit(GPIOA, keyuse);
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if(sflag==0){
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while(sflag==0){
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sflag = GPIO_ReadInputDataBit(GPIOA, keyuse);
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}
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return 1;
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}
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else{
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return 0;
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}
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}
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static void GPIO_Configuration(void)
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{
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AFIO_RemapConfig(AFIOA, GPIO_Pin_12 | GPIO_Pin_13, GPIO_FUNC_GPIO);
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void GPIO_Configuration_Steer(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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AFIO_RemapConfig(AFIOA, GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4, GPIO_FUNC_MAIN);
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AFIO_RemapConfig(AFIOA, GPIO_Pin_13, GPIO_FUNC_SECOND);
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/* GPIOA Configuration: Channel 1, 2, 3 and 4 as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void GPIO_Configuration_Steer2(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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AFIO_RemapConfig(AFIOA, GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10, GPIO_FUNC_MAIN);
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/* GPIOA Configuration: Channel 1, 2, 3 and 4 as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void TIM_STEER_CONFIG(){
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uint32_t tmpcr1;
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uint32_t tmpccmrx;
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uint32_t tmpccer;
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uint32_t tmpcr2;
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tmpcr1 = STEER_TIM->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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tmpcr1 |= (uint32_t)TIM_CR1_ARPE;
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STEER_TIM->CR1 = tmpcr1;
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/* Set the Autoreload value */
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STEER_TIM->ARR = (uint32_t)STEER_PERIOD_COUNT - 1;
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/* Set the Prescaler value */
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STEER_TIM->PSC = STEER_PRESCALER_COUNT - 1;
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STEER_TIM->RCR = 0;
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STEER_TIM->EGR = TIM_EGR_UG;
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/*PWM CH1*/
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STEER_TIM->CCER &= ~TIM_CCER_CC1E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC1M;
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tmpccmrx &= ~TIM_CCMR1_CC1S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC1P;
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/* Set the Output Compare Polarity */
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tmpccer |= TIM_OCPolarity_High;
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS1;
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/* Set the Output Idle state */
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tmpcr2 |= TIM_OCIdleState_Reset;
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/* Write to TIMx CR2 */
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STEER_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM->CCR1 = 762;
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/* Write to TIMx CCER */
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STEER_TIM->CCER = tmpccer;
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STEER_TIM->CCMR1 |= TIM_CCMR1_OC1PE;
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// PWM CH2
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STEER_TIM->CCER &= ~TIM_CCER_CC2E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC2M;
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tmpccmrx &= ~TIM_CCMR1_CC2S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC2P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 4);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS2;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 2);
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/* Write to TIMx CR2 */
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STEER_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM->CCR2 = 762;
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/* Write to TIMx CCER */
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STEER_TIM->CCER = tmpccer;
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STEER_TIM->CCMR1 |= TIM_CCMR1_OC2PE;
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// PWM CH3
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STEER_TIM->CCER &= ~TIM_CCER_CC3E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC3M;
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tmpccmrx &= ~TIM_CCMR2_CC3S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC3P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 8);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS3;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 4);
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/* Write to TIMx CR2 */
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STEER_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM->CCR3 = 762;
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/* Write to TIMx CCER */
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STEER_TIM->CCER = tmpccer;
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STEER_TIM->CCMR2 |= TIM_CCMR2_OC3PE;
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// PWM CH4
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STEER_TIM->CCER &= ~TIM_CCER_CC4E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC4M;
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tmpccmrx &= ~TIM_CCMR2_CC4S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC4P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 12);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS4;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 8);
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/* Write to TIMx CR2 */
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STEER_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM->CCR4 = 762;
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/* Write to TIMx CCER */
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STEER_TIM->CCER = tmpccer;
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STEER_TIM->CCMR2 |= TIM_CCMR2_OC4PE;
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STEER_TIM->CCER |= (uint32_t)(TIM_CCER_CC1E);
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STEER_TIM->CCER |= (uint32_t)(TIM_CCER_CC2E);
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STEER_TIM->CCER |= (uint32_t)(TIM_CCER_CC3E);
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STEER_TIM->CCER |= (uint32_t)(TIM_CCER_CC4E);
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}
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static void TIM_STEER_CONFIG2(){
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uint32_t tmpcr1;
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uint32_t tmpccmrx;
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uint32_t tmpccer;
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uint32_t tmpcr2;
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tmpcr1 = STEER_TIM2->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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tmpcr1 |= (uint32_t)TIM_CR1_ARPE;
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STEER_TIM2->CR1 = tmpcr1;
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/* Set the Autoreload value */
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STEER_TIM2->ARR = (uint32_t)STEER_PERIOD_COUNT - 1;
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/* Set the Prescaler value */
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STEER_TIM2->PSC = STEER_PRESCALER_COUNT - 1;
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STEER_TIM2->EGR = TIM_EGR_UG;
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STEER_TIM2->CCER &= ~TIM_CCER_CC1E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM2->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM2->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM2->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC1M;
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tmpccmrx &= ~TIM_CCMR1_CC1S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC1P;
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/* Set the Output Compare Polarity */
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tmpccer |= TIM_OCPolarity_High;
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS1;
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/* Set the Output Idle state */
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tmpcr2 |= TIM_OCIdleState_Reset;
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/* Write to TIMx CR2 */
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STEER_TIM2->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM2->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM2->CCR1 = 762;
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/* Write to TIMx CCER */
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STEER_TIM2->CCER = tmpccer;
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STEER_TIM2->CCMR1 |= TIM_CCMR1_OC1PE;
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STEER_TIM2->CCER &= ~TIM_CCER_CC2E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM2->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM2->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM2->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC2M;
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tmpccmrx &= ~TIM_CCMR1_CC2S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC2P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 4);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS2;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 2);
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/* Write to TIMx CR2 */
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STEER_TIM2->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM2->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM2->CCR2 = 762;
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/* Write to TIMx CCER */
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STEER_TIM2->CCER = tmpccer;
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STEER_TIM2->CCMR1 |= TIM_CCMR1_OC2PE;
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STEER_TIM2->CCER &= ~TIM_CCER_CC3E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM2->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM2->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM2->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC3M;
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tmpccmrx &= ~TIM_CCMR2_CC3S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC3P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 8);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS3;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 4);
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/* Write to TIMx CR2 */
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STEER_TIM2->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM2->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM2->CCR3 = 762;
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/* Write to TIMx CCER */
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STEER_TIM2->CCER = tmpccer;
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STEER_TIM2->CCMR2 |= TIM_CCMR2_OC3PE;
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STEER_TIM2->CCER &= ~TIM_CCER_CC4E;
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/* Get the TIMx CCER register value */
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tmpccer = STEER_TIM2->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = STEER_TIM2->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = STEER_TIM2->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC4M;
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tmpccmrx &= ~TIM_CCMR2_CC4S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC4P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 12);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS4;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 8);
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/* Write to TIMx CR2 */
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STEER_TIM2->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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STEER_TIM2->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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STEER_TIM2->CCR4 = 762;
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/* Write to TIMx CCER */
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STEER_TIM2->CCER = tmpccer;
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STEER_TIM2->CCMR2 |= TIM_CCMR2_OC4PE;
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STEER_TIM2->CCER |= (uint32_t)(TIM_CCER_CC1E);
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STEER_TIM2->CCER |= (uint32_t)(TIM_CCER_CC2E);
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STEER_TIM2->CCER |= (uint32_t)(TIM_CCER_CC3E);
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STEER_TIM2->CCER |= (uint32_t)(TIM_CCER_CC4E);
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}
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static int tim_steer_test(void)
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{
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printf("\n\rSTEER TEST\n\r");
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GPIO_Configuration();
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GPIO_Configuration_Steer();
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GPIO_Configuration_Steer2();
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TIM_STEER_CONFIG();
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TIM_STEER_CONFIG2();
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STEER_TIM->BDTR|=(TIM_BDTR_MOE);
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STEER_TIM->CR1|=TIM_CR1_CEN;
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STEER_TIM2->CR1|=TIM_CR1_CEN;
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return 0;
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}
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int tim_steer(int argc, void *argv[])
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{
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tim_steer_test();
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return 0;
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}
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int angle_set(int argc, void *argv[])
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{
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if (argc != 3)
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{
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printf("\n usage: angle set <channel:1-8> <angle:0-180>\n");
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return 1;
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}
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uint32_t channel = str2num(argv[1]);
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uint32_t angle = str2num(argv[2]);
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uint32_t data;
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if(angle > 180){
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angle = 180;
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}
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else if(angle < 0){
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angle = 0;
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}
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data = (254 + ((1270000-254000)/180*angle)/1000);
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//data = (uint32_t)(254.0 + ((1270.0-254.0)/180.0*angle));
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switch(channel){
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case 1: STEER_TIM->CCR1 = data; break;
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case 2: STEER_TIM->CCR2 = data; break;
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case 3: STEER_TIM->CCR3 = data; break;
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case 4: STEER_TIM->CCR4 = data; break;
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case 5: STEER_TIM2->CCR1 = data; break;
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case 6: STEER_TIM2->CCR2 = data; break;
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case 7: STEER_TIM2->CCR3 = data; break;
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case 8: STEER_TIM2->CCR4 = data; break;
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}
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return 0;
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}
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int angle_keyset(int argc, void *argv[])
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{
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if (argc != 2)
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{
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printf("\n usage: angle keyset <channel:1-8>\n");
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return 1;
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}
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|
|
uint32_t channel = str2num(argv[1]);
|
|
volatile uint32_t ChannelPulse = 762;
|
|
int i = 0;
|
|
|
|
switch(channel){
|
|
case 1: ChannelPulse = STEER_TIM->CCR1; break;
|
|
case 2: ChannelPulse = STEER_TIM->CCR2; break;
|
|
case 3: ChannelPulse = STEER_TIM->CCR3; break;
|
|
case 4: ChannelPulse = STEER_TIM->CCR4; break;
|
|
case 5: ChannelPulse = STEER_TIM2->CCR1; break;
|
|
case 6: ChannelPulse = STEER_TIM2->CCR2; break;
|
|
case 7: ChannelPulse = STEER_TIM2->CCR3; break;
|
|
case 8: ChannelPulse = STEER_TIM2->CCR4; break;
|
|
}
|
|
|
|
while(1){
|
|
char c;
|
|
c = x_getchar();
|
|
if (c == 0x3) break;
|
|
|
|
if(scan_key(KEY0)){
|
|
ChannelPulse += 20;
|
|
if(ChannelPulse > 1270){
|
|
ChannelPulse = 1270;
|
|
}
|
|
}
|
|
else if (scan_key(KEY1)){
|
|
ChannelPulse -= 20;
|
|
if(ChannelPulse < 254){
|
|
ChannelPulse = 254;
|
|
}
|
|
}
|
|
|
|
switch(channel){
|
|
case 1: STEER_TIM->CCR1 = ChannelPulse; break;
|
|
case 2: STEER_TIM->CCR2 = ChannelPulse; break;
|
|
case 3: STEER_TIM->CCR3 = ChannelPulse; break;
|
|
case 4: STEER_TIM->CCR4 = ChannelPulse; break;
|
|
case 5: STEER_TIM2->CCR1 = ChannelPulse; break;
|
|
case 6: STEER_TIM2->CCR2 = ChannelPulse; break;
|
|
case 7: STEER_TIM2->CCR3 = ChannelPulse; break;
|
|
case 8: STEER_TIM2->CCR4 = ChannelPulse; break;
|
|
}
|
|
|
|
i++;
|
|
if(i==100000){
|
|
i = 0;
|
|
printf(".");
|
|
}
|
|
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int tim_set_steer(int argc, void *argv[])
|
|
{
|
|
if (argc != 4)
|
|
{
|
|
printf("\n usage: tim set <0:atim/1:gtim> <psc> <arr>\n");
|
|
return 1;
|
|
}
|
|
|
|
uint32_t tim_choice = str2num(argv[1]);
|
|
uint32_t psc_in = str2num(argv[2]);
|
|
uint32_t arr_in = str2num(argv[2]);
|
|
uint32_t data;
|
|
|
|
|
|
switch(tim_choice){
|
|
case 1: STEER_TIM->PSC = psc_in; STEER_TIM->ARR = arr_in; break;
|
|
case 2: STEER_TIM2->PSC = psc_in; STEER_TIM2->ARR = arr_in; break;
|
|
}
|
|
return 0;
|
|
}
|