462 lines
12 KiB
C
462 lines
12 KiB
C
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//#include "ls1c103.h"
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#include "ls1x.h"
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#include "ls1x_gpio.h"
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#include "test.h"
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#include "ls1x_gpio.h"
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#include "ls1c103_map.h"
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#include "ls1c103_tim.h"
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#include "ls1c103_dcm_tim.h"
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#include "Config.h"
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static int err;
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volatile int Encoder_Overflow_Count = 0;
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static dcm_motor_dir_t direction; // dir
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static uint16_t dutyfactor; // speed
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extern INT8U x_getchar(void);
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extern unsigned int str2num(unsigned char *);
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static uint8_t scan_key(uint32_t key){
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uint16_t keyuse;
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if(key == KEY1){
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keyuse = GPIO_Pin_13;
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}
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else{
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keyuse = GPIO_Pin_12;
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}
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uint8_t sflag = GPIO_ReadInputDataBit(GPIOA, keyuse);
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if(sflag==0){
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while(sflag==0){
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sflag = GPIO_ReadInputDataBit(GPIOA, keyuse);
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}
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return 1;
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}
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else{
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return 0;
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}
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}
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static void GPIO_Configuration(void)
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{
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AFIO_RemapConfig(AFIOA, GPIO_Pin_12 | GPIO_Pin_13, GPIO_FUNC_GPIO);
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void GPIO_Configuration_DCM(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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AFIO_RemapConfig(AFIOA, GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4, GPIO_FUNC_MAIN);
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AFIO_RemapConfig(AFIOA, GPIO_Pin_13, GPIO_FUNC_SECOND);
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/* GPIOA Configuration: Channel 1, 2, 3 and 4 as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void GPIO_Configuration_ENCODER(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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AFIO_RemapConfig(AFIOA, GPIO_Pin_7 | GPIO_Pin_8, GPIO_FUNC_MAIN);
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/* GPIOA Configuration: Channel 1, 2, 3 and 4 as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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static void TIM_DCM_CONFIG(){
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uint32_t tmpcr1;
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uint32_t tmpccmrx;
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uint32_t tmpccer;
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uint32_t tmpcr2;
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tmpcr1 = DCM_TIM->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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tmpcr1 |= (uint32_t)TIM_CR1_ARPE;
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DCM_TIM->CR1 = tmpcr1;
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/* Set the Autoreload value */
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DCM_TIM->ARR = (uint32_t)DCM_PERIOD_COUNT - 1;
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/* Set the Prescaler value */
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DCM_TIM->PSC = DCM_PRESCALER_COUNT - 1;
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DCM_TIM->RCR = 0;
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DCM_TIM->EGR = TIM_EGR_UG;
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DCM_TIM->CCER &= ~TIM_CCER_CC1E;
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/* Get the TIMx CCER register value */
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tmpccer = DCM_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = DCM_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = DCM_TIM->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC1M;
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tmpccmrx &= ~TIM_CCMR1_CC1S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC1P;
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/* Set the Output Compare Polarity */
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tmpccer |= TIM_OCPolarity_High;
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS1;
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/* Set the Output Idle state */
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tmpcr2 |= TIM_OCIdleState_Reset;
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/* Write to TIMx CR2 */
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DCM_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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DCM_TIM->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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DCM_TIM->CCR1 = 0;
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/* Write to TIMx CCER */
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DCM_TIM->CCER = tmpccer;
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DCM_TIM->CCMR1 |= TIM_CCMR1_OC1PE;
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DCM_TIM->CCER &= ~TIM_CCER_CC2E;
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/* Get the TIMx CCER register value */
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tmpccer = DCM_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = DCM_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = DCM_TIM->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC2M;
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tmpccmrx &= ~TIM_CCMR1_CC2S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC2P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 4);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS2;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 2);
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/* Write to TIMx CR2 */
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DCM_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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DCM_TIM->CCMR1 = tmpccmrx;
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/* Set the Capture Compare Register value */
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DCM_TIM->CCR2 = 0;
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/* Write to TIMx CCER */
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DCM_TIM->CCER = tmpccer;
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DCM_TIM->CCMR1 |= TIM_CCMR1_OC2PE;
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DCM_TIM->CCER &= ~TIM_CCER_CC3E;
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/* Get the TIMx CCER register value */
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tmpccer = DCM_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = DCM_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = DCM_TIM->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC3M;
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tmpccmrx &= ~TIM_CCMR2_CC3S;
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCMode_PWM1;
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC3P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 8);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS3;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 4);
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/* Write to TIMx CR2 */
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DCM_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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DCM_TIM->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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DCM_TIM->CCR3 = 0;
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/* Write to TIMx CCER */
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DCM_TIM->CCER = tmpccer;
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DCM_TIM->CCMR2 |= TIM_CCMR2_OC3PE;
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DCM_TIM->CCER &= ~TIM_CCER_CC4E;
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/* Get the TIMx CCER register value */
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tmpccer = DCM_TIM->CCER;
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/* Get the TIMx CR2 register value */
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tmpcr2 = DCM_TIM->CR2;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = DCM_TIM->CCMR2;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR2_OC4M;
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tmpccmrx &= ~TIM_CCMR2_CC4S;
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/* Select the Output Compare Mode */
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tmpccmrx |= (TIM_OCMode_PWM1 << 8);
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC4P;
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/* Set the Output Compare Polarity */
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tmpccer |= (TIM_OCPolarity_High << 12);
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/* Reset the Output Compare IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS4;
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/* Set the Output Idle state */
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tmpcr2 |= (TIM_OCIdleState_Reset << 8);
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/* Write to TIMx CR2 */
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DCM_TIM->CR2 = tmpcr2;
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/* Write to TIMx CCMR1 */
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DCM_TIM->CCMR2 = tmpccmrx;
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/* Set the Capture Compare Register value */
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DCM_TIM->CCR4 = 0;
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/* Write to TIMx CCER */
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DCM_TIM->CCER = tmpccer;
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DCM_TIM->CCMR2 |= TIM_CCMR2_OC4PE;
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DCM_TIM->CCER |= (uint32_t)(TIM_CCER_CC1E);
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DCM_TIM->CCER |= (uint32_t)(TIM_CCER_CC2E);
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DCM_TIM->CCER |= (uint32_t)(TIM_CCER_CC3E);
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DCM_TIM->CCER |= (uint32_t)(TIM_CCER_CC4E);
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}
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static void TIM_ENCODER_CONFIG(void)
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{
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uint32_t tmpcr1;
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uint32_t tmpsmcr;
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uint32_t tmpccmr1;
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uint32_t tmpccer;
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ENCODER_TIM->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
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/* Configure the Time base in the Encoder Mode */
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tmpcr1 = ENCODER_TIM->CR1;
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tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
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tmpcr1 |= TIM_CounterMode_Up;
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tmpcr1 &= ~TIM_CR1_CKD;
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tmpcr1 |= (uint32_t)TIM_CKD_DIV1;
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ENCODER_TIM->CR1 = tmpcr1;
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/* Set the Autoreload value */
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ENCODER_TIM->ARR = (uint32_t)ENCODER_TIM_PERIOD - 1 ;
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/* Set the Prescaler value */
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ENCODER_TIM->PSC = ENCODER_TIM_PRESCALER;
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ENCODER_TIM->RCR = 0;
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ENCODER_TIM->EGR = TIM_EGR_UG;
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/* Get the TIMx SMCR register value */
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tmpsmcr = ENCODER_TIM->SMCR;
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/* Get the TIMx CCMR1 register value */
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tmpccmr1 = ENCODER_TIM->CCMR1;
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/* Get the TIMx CCER register value */
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tmpccer = ENCODER_TIM->CCER;
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/* Set the encoder Mode */
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tmpsmcr |= TIM_EncoderMode_TI12;
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/* Select the Capture Compare 1 and the Capture Compare 2 as input */
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tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
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tmpccmr1 |= (TIM_ICSelection_DirectTI | (TIM_ICSelection_DirectTI << 8U));
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/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
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tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
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tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
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tmpccmr1 |= TIM_ICPSC_DIV1 | (TIM_ICPSC_DIV1 << 8U);
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tmpccmr1 |= (0 << 4U) | (0 << 12U);
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/* Set the TI1 and the TI2 Polarities */
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tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
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tmpccer |= TIM_ICPolarity_Rising | (TIM_ICPolarity_Rising << 4U);
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/* Write to TIMx SMCR */
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ENCODER_TIM->SMCR = tmpsmcr;
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/* Write to TIMx CCMR1 */
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ENCODER_TIM->CCMR1 = tmpccmr1;
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/* Write to TIMx CCER */
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ENCODER_TIM->CCER = tmpccer;
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ENCODER_TIM->CNT = 0;
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ENCODER_TIM->SR = ~(TIM_IT_Update);
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ENCODER_TIM->DIER |= (TIM_IT_Update);
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ENCODER_TIM->CR1|= TIM_CR1_URS;
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/* Reset the CCxE Bit */
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ENCODER_TIM->CCER &= ~TIM_CCER_CC1E;
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/* Set or reset the CCxE Bit */
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ENCODER_TIM->CCER |= TIM_CCER_CC1E; /* 0x1FU = 31 bits max shift */
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/* Reset the CCxE Bit */
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ENCODER_TIM->CCER &= ~TIM_CCER_CC2E;
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/* Set or reset the CCxE Bit */
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ENCODER_TIM->CCER |= TIM_CCER_CC2E; /* 0x1FU = 31 bits max shift */
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ENCODER_TIM->CR1 |= (TIM_CR1_CEN);
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}
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static void set_motor_speed(void)
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{
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if (direction == DCM_MOTOR_FWD)
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{
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DCM_TIM->CCR2 = 0;
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DCM_TIM->CCR1 = dutyfactor;
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}
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else
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{
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DCM_TIM->CCR1 = 0;
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DCM_TIM->CCR2 = dutyfactor;
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}
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}
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extern void irq_motor_init(int index);
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static int tim_dcm_enc_test(void)
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{
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volatile int ChannelPulse = 0;
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int i = 0;
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direction = DCM_MOTOR_FWD; // dir
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dutyfactor = 0;
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printf("\n\rDCM ENC TEST\n\r");
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GPIO_Configuration();
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GPIO_Configuration_DCM();
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GPIO_Configuration_ENCODER();
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TIM_DCM_CONFIG();
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TIM_ENCODER_CONFIG();
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dcm_mode = DCM_ENC;
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Encoder_Overflow_Count = 0;
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irq_motor_init(0);
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while(1){
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if(scan_key(KEY0)){
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printf("start\n\r");
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DCM_TIM->BDTR|=(TIM_BDTR_MOE);
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DCM_TIM->CR1|=TIM_CR1_CEN;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int tim_dcm_enc(int argc, void *argv[])
|
||
|
|
{
|
||
|
|
tim_dcm_enc_test();
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
int enc_speed_set(int argc, void *argv[])
|
||
|
|
{
|
||
|
|
if (argc != 3)
|
||
|
|
{
|
||
|
|
printf("\n usage: speed set <dir:0/1> <speed:0-900>\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t dir = str2num(argv[1]);
|
||
|
|
uint32_t speed = str2num(argv[2]);
|
||
|
|
|
||
|
|
if(dcm_mode != DCM_ENC){
|
||
|
|
printf("\n\rNOT IN ENC MOTOR MODE!\n\r");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if(speed > 900){
|
||
|
|
speed = 900;
|
||
|
|
}
|
||
|
|
else if(speed < 0){
|
||
|
|
speed = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if(dir == 0){
|
||
|
|
direction = DCM_MOTOR_FWD;
|
||
|
|
}
|
||
|
|
else{
|
||
|
|
direction = DCM_MOTOR_REV;
|
||
|
|
}
|
||
|
|
|
||
|
|
dutyfactor = speed;
|
||
|
|
|
||
|
|
if (direction == DCM_MOTOR_FWD)
|
||
|
|
{
|
||
|
|
DCM_TIM->CCR2 = 0; DCM_TIM->CCR1 = dutyfactor;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
DCM_TIM->CCR1 = 0; DCM_TIM->CCR2 = dutyfactor;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int enc_speed_keyset(int argc, void *argv[])
|
||
|
|
{
|
||
|
|
volatile int ChannelPulse = 0;
|
||
|
|
int i = 0;
|
||
|
|
direction = DCM_MOTOR_FWD; // dir
|
||
|
|
dutyfactor = 0;
|
||
|
|
|
||
|
|
if(dcm_mode != DCM_ENC){
|
||
|
|
printf("\n\rNOT IN ENC MOTOR MODE!\n\r");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
while(1){
|
||
|
|
if(scan_key(KEY0)){
|
||
|
|
ChannelPulse += 20;
|
||
|
|
if(ChannelPulse > 900){
|
||
|
|
ChannelPulse = 900;
|
||
|
|
}
|
||
|
|
if(ChannelPulse >= 0){
|
||
|
|
dutyfactor = ChannelPulse;
|
||
|
|
direction = DCM_MOTOR_FWD;
|
||
|
|
}
|
||
|
|
else{
|
||
|
|
dutyfactor = -ChannelPulse;
|
||
|
|
direction = DCM_MOTOR_REV;
|
||
|
|
}
|
||
|
|
set_motor_speed();
|
||
|
|
}
|
||
|
|
else if (scan_key(KEY1)){
|
||
|
|
ChannelPulse -= 20;
|
||
|
|
if(ChannelPulse < -900){
|
||
|
|
ChannelPulse = -900;
|
||
|
|
}
|
||
|
|
if(ChannelPulse >= 0){
|
||
|
|
dutyfactor = ChannelPulse;
|
||
|
|
direction = DCM_MOTOR_FWD;
|
||
|
|
}
|
||
|
|
else{
|
||
|
|
dutyfactor = -ChannelPulse;
|
||
|
|
direction = DCM_MOTOR_REV;
|
||
|
|
}
|
||
|
|
set_motor_speed();
|
||
|
|
}
|
||
|
|
|
||
|
|
char c;
|
||
|
|
c = x_getchar();
|
||
|
|
if (c == 0x3) break;
|
||
|
|
i++;
|
||
|
|
if(i==100000){
|
||
|
|
i = 0;
|
||
|
|
printf(".");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int show_local(){
|
||
|
|
int mylocal;
|
||
|
|
int decimal;
|
||
|
|
mylocal = Encoder_Overflow_Count;
|
||
|
|
//decimal = (int)((float)ENCODER_TIM->CNT/ENCODER_TIM_PERIOD*100.0)%100;
|
||
|
|
decimal = (int)(ENCODER_TIM->CNT/ENCODER_TIM_PERIOD*100)%100;
|
||
|
|
printf("\n\rNow loc:%d.%d\n\r",mylocal,decimal);
|
||
|
|
}
|
||
|
|
|
||
|
|
|