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Add program, package and interface to systemverilog scopes (#888)
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Tarik Graba 2024-07-27 18:31:10 +02:00 committed by GitHub
parent 1690b19ea6
commit bc087d88de
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1 changed files with 6 additions and 0 deletions
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6
autoload/tagbar/types/uctags.vim
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@ -1372,11 +1372,17 @@ function! tagbar#types#uctags#init(supported_types) abort
\ 'E' : 'enum',
\ 'C' : 'class',
\ 'm' : 'module',
\ 'P' : 'program',
\ 'K' : 'package',
\ 'I' : 'interface',
\ }
let type_systemverilog.scope2kind = {
\ 'enum' : 'E',
\ 'class' : 'C',
\ 'module' : 'm',
\ 'program' : 'P',
\ 'package' : 'K',
\ 'interface': 'I',
\ }
let types.systemverilog = type_systemverilog
" VHDL {{{1